1. Field of the Invention
The invention relates to the formation of integrated circuit devices, and specifically to improvements in the process used to manufacture connecting metals in such devices.
2. Description of the Related Art
As integrated circuit device manufacturers continually strive to integrate ever more device components into limited chip sizes, device interconnects have increasingly become an important design consideration. Essentially, such interconnects comprise the "wiring" for the component parts of the circuits on such chip by coupling the components to other such components in the overall device. Indeed, in ultra large scale integration (ULSI) devices having dimensions on the order of 1 micron or less, interconnects define the limits in performance, density and reliability, and are thus required to have very low electrical resistivity and high reliability.
Interconnect structures are generally desired to have good adhesion to the top surface of the wafer (which generally comprises a dielectric layer such as SiO.sub.2), be relatively easy to pattern, be of high purity, and make good electrical contact with the wafer material. A number of different metals, (most often aluminum), composite materials, (such as aluminum/silicon/copper alloys and refractory metal silicides), and doped polysilicon, have all been utilized as interconnects, each having various advantages and disadvantages.
Various methods of depositing such interconnects on the wafer surface have been utilized. One desirable processing technique is chemical vapor deposition (CVD). CVD offers such advantages as the use of low maintenance machinery, the provision of conformal step coverage, and high speed production. However, in utilizing CVD to deposit metal layers for use as interconnects, it has been found that the resulting cross-sectional profile of the deposited metal interconnect layer is generally hemispherical in form. A hemispherical profile reduces the integration efficiency of the interconnect since excess lateral area is required for the amount of interconnect material. Thus, it is desirable that the edge profile of the interconnect lines be vertical, or nearly vertical, to improve the packaging density of the integrated circuit device and to improve isolation of the interconnects. This criticality is enhanced by the decrease in spacing between the lines which follows from increased integration.
Copper is a material which has been suggested for use as an interconnect since it achieves many of the above-mentioned desirable interconnect characteristics. As noted in an article entitled "New OMCVD Precursors For Selective Copper Metallization", Norman et al., IEEE No. TH-0359-0/91/0000-0123, (Jun. 11-12, 1991 VMIC Conference), copper interconnects may be selectively deposited in low temperature CVD processes, making the use of copper attractive from a manufacturing point of view as well. In general, the process of depositing copper as an interconnect involves first depositing a selective nucleation layer to provide for selective deposition of copper. A number of materials are suitable for use as the nucleating layer, such as tungsten, titanium nitride, and tantalum are suitable for this purpose.
Attempts to control the hemispherical profile of copper using sidewall barriers have also been suggested. The article entitled "Encapsulated Copper Interconnection Devices Using Sidewall Barriers," Gardner, et al. IEEE No. TH-0359-0/091/0000-0099, (Jun. 11-12, 1991 VMIC Conference), describes an interconnect structure wherein copper is encapsulated by an upper and lower layer of barrier material, and wherein sidewall barriers are used to prevent lateral or horizontally oriented hillocks. The method disclosed therein involves (a) providing a layer of barrier material over the dielectric material overlying a wafer surface; (b) providing a low resistivity conductor (such as copper) over the barrier layer; (c) providing a second layer of barrier material over the low resistivity material; (d) patterning the composite layer by dry etch or (for copper) ion milling followed by dry etching; and finally (e) forming sidewall barriers by (1) depositing a thin layer of molybdenum or SiN, and (2) anisotropic etching to leave sidewall material. While the aforementioned process achieves the results desired of a interconnect while preventing lateral diffusion, the method chosen for fabrication involves a significant number of steps resulting in increased costs to achieve the desired results of an improved interconnect structure.